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Algorithms get pampered by Microcontrollers, Gate Arrays and EPROMs July 6, 2009

Posted by jbarseneau in Uncategorized.
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A while back a handful of companies addressed their computational scalability by looking at the processing units they were using– and they looked very closely. These players in hardware acceleration are still speaking to Wall Street customers. In messaging, you have Tervela and, a secondary player, you have Xambala, which put a parser on a chip, and thirdly ACTIV Financial demonstrated its solution — a ticker plant coded directly into a silicon chip.

The electrical and electronic engineers that have design and develop Central Microprocessing Units (CPUs) know that if anyone had a single repeatable function that was required to be computed by the CPU, it may perform its job much quicker if the CPU went on a “physics” diet. i.e. slim it down, throw it all out in the garbage, clean out the attic and downsize the house; reduced instruction sets, optimized on chip memory and so on. Well all of the three companies have done that. Either for routing purposes or a hardwired ticker plant, companies are going “hard” wired for EPROMs, Gate Arrays, and custom ICs.

More to Come…

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1. jbarseneau - July 9, 2009

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